SK hynix set out plans on 14 October to develop 3D stacked DRAM and High Bandwidth Flash alongside HBM, targeting about 10 times the capacity of comparable-generation HBM for the flash product at roughly half its bandwidth, The Korea Herald reported.
Key points
- SK hynix is developing stacked DRAM and High Bandwidth Flash for AI workloads that need to move data between memory and storage.
- Ahn Hyun projected roughly 19-fold growth in AI infrastructure performance requirements by 2030 from 2026, according to The Korea Herald. Korea IT Times reported the estimate as approximately 20-fold.
- The company targets about 10 times comparable-generation HBM capacity for High Bandwidth Flash, at roughly half the bandwidth.
Ahn Hyun’s 2030 infrastructure projection
Ahn Hyun, SK hynix’s president and chief development officer, presented the roadmap during a keynote at SEDEX 2026 in Seoul on 14 October. He projected that AI infrastructure performance requirements could grow roughly 19-fold by 2030 compared with 2026, according to The Korea Herald. Korea IT Times reported the company’s estimate as approximately 20-fold over the same period.
Ahn linked rising demand for inference capacity to more complex tasks, longer context windows and greater request volumes. He described a shift in the memory problem: data must move among HBM, conventional DRAM and solid-state drives, with delays and energy costs arising between those layers. SK hynix plans to work across that hierarchy while continuing to develop HBM, including versions tailored to customers’ AI architectures.
Korea IT Times reported that key-value caches, which retain information for reuse, require more capacity as context windows lengthen. The company’s roadmap also includes custom HBM that incorporates memory controllers and customer-specific logic into its base die. Those changes are intended to match memory more closely to individual AI systems.
The wider approach has a counterpart at another Korean memory maker. AI Affairs reported Samsung’s strategy spanning HBM5, CXL and SSDs. SK hynix is likewise pursuing Compute Express Link and further storage technologies as part of its work on data movement across AI systems.
Stacked DRAM and High Bandwidth Flash
SK hynix’s proposed 3D stacked DRAM places memory above processors, including graphics and neural processing units. Shortening the physical route for data is intended to increase processing speed and reduce power use. The design addresses movement between a processor and nearby memory, while the company’s flash work targets greater capacity elsewhere in the system.
High Bandwidth Flash, or HBF, applies stacking and high-speed data-transfer techniques developed for HBM to NAND flash. Korea IT Times described those techniques as through-silicon via stacking and high-speed input/output. SK hynix targets around 10 times the capacity of HBM from the same generation, with bandwidth of approximately half as much.
SK hynix sees a potential use for HBF in inference workloads that read large amounts of data repeatedly but perform relatively fewer writes. The company expects it to reduce reliance on DRAM and solid-state drive access. Ahn also called for HBF standards and cooperation with global technology partners as SK hynix develops the product.
At SEDEX, SK hynix displayed server DRAM and enterprise solid-state drives alongside PC and mobile memory products. The exhibition also included an Nvidia Vera Rubin superchip and an HBM wafer signed by Nvidia chief executive Jensen Huang.
MARS and the HBF sampling timetable
SK hynix presented a separate approach to inference memory at the OCP Global Summit 2026. Senior Vice President Hoshik Kim described MARS, a rack-scale system designed to pool memory for use across computing resources, TrendForce reported on 13 October.
Kim said the system had delivered a three- to fivefold improvement in time to first token against recomputation in a multi-turn AI inference application. He attributed the result to storing the application’s growing key-value cache in shared memory without exhausting GPU memory and storage. Kim also said that tying memory expansion to whole server nodes could lead operators to buy more GPUs than required, raising their total cost of ownership.
For HBF, Kim described a capacity target of about 14 times HBM’s, at half its bandwidth, TrendForce reported. SK hynix released version 0.7 of an OCP HBF specification in July 2026, Kim said. SK hynix expects to release version 1.0 in early 2027 and sample an HBF Cube in early 2028, according to his remarks reported by TrendForce.
