Synopsys and TSMC announced an expanded collaboration on 23 September covering A14-certified EDA flows with agentic AI capabilities, multi-die CoWoS support, co-packaged optics enablement, and a broadened 2nm IP portfolio for AI and HPC chips, according to a press release from Synopsys.
Key points
- Certified EDA flows on TSMC A14 are now available across digital and analog domains with agentic AI capabilities enabled.
- Agentic AI workflows using Custom Compiler and Fusion Compiler automate analog, digital and multi-die design tasks with LLM-assisted analysis.
- 3DIC Compiler adds agentic AI chiplet floorplan co-optimization for TSMC 3DFabric and enables IVR co-design and simulation on CoWoS.
- On N2P, Synopsys achieved IP enablement and tape-out milestones for PCIe 7.0, HBM4, LPDDR6/5X/5, 224G Ethernet PHY, UCIe, OTP and advanced SLM PVT monitoring IP.
- UCIe-A 32G/40G silicon demonstrated on TSMC N3P test chip with CoWoS-S interposer; 64G UCIe IP tape-outs completed on both 2nm and 3nm nodes.
A14-certified EDA flows with agentic AI
The companies have certified Synopsys digital and analog implementation-through-signoff flows on TSMC’s A14 process, with agentic AI capabilities now enabled across the flow. In analog design, device routing enablement on A14 marks a milestone for advanced analog place-and-route automation, boosting layout productivity and accelerating adoption of the node. Synopsys Custom Compiler accelerates analog migration, while Fusion Compiler uses LLM-assisted analysis to improve digital design productivity.
Agentic AI chiplet floorplan co-optimization for 3DFabric
A new agentic AI chiplet floorplan co-optimization flow in Synopsys 3DIC Compiler automates complex floorplanning tasks for heterogeneous multi-die designs, accelerating design convergence on TSMC 3DFabric technologies.
IVR co-design on CoWoS and COUPE optics enablement
Synopsys 3DIC Compiler now enables co-design and simulation of integrated voltage regulators on TSMC CoWoS technology in a unified environment, addressing power integrity and thermal requirements for multi-die AI systems. The companies are also continuing joint enablement for TSMC COUPE technology, providing an integrated photonic-electronic co-design flow spanning 3DIC implementation, multiphysics analysis and optimisation for co-packaged optics development.
N2P IP milestones and UCIe validation
On TSMC’s N2P process, Synopsys reached IP enablement and tape-out milestones for a suite of high-speed interfaces and memory IP including PCIe 7.0, HBM4, LPDDR6/5X/5, 224G Ethernet PHY, UCIe, OTP and advanced SLM process, voltage and temperature monitoring IP. The company demonstrated UCIe-A 32G/40G silicon on an N3P test chip integrated with a CoWoS-S interposer, validating high-speed die-to-die connectivity. Synopsys also completed 64G UCIe IP tape-outs on both 2nm and 3nm nodes, with embedded DFT capabilities for in-system visibility.
Michael Buehler-Garcia, senior vice president at Synopsys, said the joint innovations address the continuum of silicon-to-systems co-design capabilities needed for next-generation AI and HPC. Aveek Sarkar, director of the Ecosystem and Alliance Management Division at TSMC, said combining certified EDA solutions and silicon-proven IP with TSMC’s latest process and packaging innovations enables customers to push the boundaries of performance, integration and energy efficiency.
