ChangXin Memory Technologies (CXMT) said its sixth-generation DRAM platform uses a 4F² cell layout and has passed engineering-sample verification, against the mainstream 6F² design, Pandaily reported. The statement appeared in an investor relations record published on 31 October. CXMT expects to send its first 4F² product to customers by the end of 2026, putting a customer-testing date on a design Micron has rejected as a route to higher memory density.
Key points
- CXMT says its 4F² platform has passed engineering-sample checks. Customer samples are expected by the end of 2026.
- Volume production depends on customer validation and market demand, according to CXMT.
- Micron intends to retain 6F² and pursue 3D DRAM. Samsung and SK hynix are developing 4F² designs.
CXMT puts customer samples after engineering checks
Engineering-sample verification and customer sampling are separate steps in CXMT’s timetable. The company said volume production would follow customer validation and market demand. Its 31 October record therefore places the sixth-generation platform beyond an internal check, while making production conditional on how the product performs with buyers.
A DRAM cell contains a transistor and a capacitor. Cell area is expressed in F², with F representing the smallest feature a fabrication process can print. The mainstream 6F² layout measures 3F by 2F, while 4F² measures 2F by 2F, Sammy Fans reported. A 4F² design puts the transistor channel vertically rather than alongside the other parts of the cell.
CXMT’s design uses a Vertical Surrounded Gate transistor. The company says it has more than 300 published patent families covering 4F² technology. On 10 October, CXMT president Cao Kanyu said the company planned to unveil a server DDR5 RDIMM using a 4F² cell by the end of 2026. That module announcement and the subsequent timetable for customer samples concern different milestones.
CXMT described higher bit density as a problem involving word lines, bit lines and capacitors, all of which need space. It said architectures also carry different costs for process integration, lithography steps and thermal budget at a given node. Existing production lines, patent holdings and spending structures help determine which approach a manufacturer chooses, the company said.
Micron keeps 6F² in its DRAM roadmap
Micron President and Chief Technology and Products Officer Scott DeBoer set out the opposing approach at a company technology webinar on 21 October. Micron will continue developing 6F² and pursue 3D DRAM rather than adopt 4F², he said. DeBoer said Micron had studied the smaller layout for more than 20 years without finding a workable way to scale it.
In DeBoer’s assessment, capacitor spacing and size determine the theoretical density limit, rather than the transistor’s layout. Micron also pointed to the complexity and cost of making 4F² cells and to scaling difficulties at more advanced nodes. That position puts manufacturing cost alongside cell area in the choice between the two designs.
CXMT’s stated route does not depend on shrinking printed line widths to reduce the cell’s area factor from 6 to 4. Its approach instead changes the layout while using dimensions reachable with DUV lithography. The company’s customer-validation condition leaves the manufacturing decision tied to the performance of products made with that architecture.
Samsung and SK hynix test 4F² routes
Samsung showed a 16Gb 4F² prototype at ISSCC 2026 using vertical channel transistors and wafer-to-wafer hybrid bonding. It plans to apply 4F² at its 10a, 10b and 10c nodes before moving to 3D DRAM at 10d. Pandaily reported that Samsung semiconductor CTO Song Jai-hyuk said on 12 October that 4F² work was continuing. Samsung chief technology officer Song Jae-hyuk confirmed development at SEDEX 2026 on 14 October, Sammy Fans reported.
SK hynix is developing a vertical-gate design that it says improves bit density by more than 20%. It verified read and write operations on 4F² test arrays in July. SK hynix plans to present a paper on a capacitorless 4F² design at IEDM in December.
