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Monday 28 September 2026

Technology

ASM launches flowable carbon process to fill and level chip features

The company says its XP8 Vertos process could replace separate wafer-smoothing steps, has entered high-volume manufacturing and is applicable to both logic and memory devices.

Scientist in protective gear walking through a modern cleanroom laboratory environment
Photo: Российский центр гибкой электроники via Pexels

ASM launched XP8 Vertos Flowable Carbon on 22 September 2026, introducing a plasma-enhanced chemical vapour deposition process that the company says fills narrow features in semiconductor wafers and leaves their surfaces level in the same operation. ASM, based in Almere in the Netherlands, makes wafer-processing equipment. Its proposed gain is in the sequence of manufacturing steps: the company says the process can remove the need for subsequent polishing or etch-back.

Key points

  • ASM says the carbon film fills gaps and levels the wafer surface in one deposition process.
  • The company says this could replace later chemical mechanical planarisation or etch-back steps.
  • ASM says the technology has entered high-volume manufacturing and can be used for logic and memory devices.

Vertos fills gaps from the bottom

A chip wafer is built up through successive layers, and the shapes etched into one layer affect the surface on which the next must be patterned. ASM says conventional carbon films follow the contours of those shapes as they are deposited. A deep, narrow opening can therefore leave a depression at the surface, calling for another operation to make the wafer flat enough for the next stage.

Vertos is intended to change how the material settles. Tyler Sample, ASM’s Vice President PECVD Key Product Unit Head, says its carbon film flows into a feature and fills it from the bottom upwards. Rather than reproducing the uneven shape below, the deposited material levels itself across the wafer, according to ASM. The physical distinction is much like filling a groove with a material that settles flat instead of lining the groove with a coating of even thickness.

ASM says the process can fill high-aspect-ratio features — openings deep in relation to their width — without leaving voids or seams. Those properties matter to the company’s account of the process because an apparently level top surface would be of little use if the material inside a feature contained gaps. ASM also says the film produces a uniform surface for the following patterning operation.

Running a computer programme could depend on chips made with fewer separate wafer-smoothing steps if this process were used in their manufacture. That possibility follows from ASM’s proposed combination of filling and levelling, rather than from a change to what the programme does.

ASM puts levelling inside PECVD

The deposition method is plasma-enhanced chemical vapour deposition, or PECVD. It forms a film on a wafer using gases and a plasma; in ASM’s account, the resulting carbon material has enough flowability to enter patterned openings while forming a level surface. The company says both jobs take place in one PECVD system, rather than in a deposition stage followed by a separate surface-correction stage.

The separate stages ASM wants to avoid are chemical mechanical planarisation, which polishes a wafer’s surface, and etch-back, which removes deposited material. ASM says removing those downstream operations would reduce process complexity, manufacturing costs and the risk of defects.

ASM also attributes greater thermal stability and area-selective deposition characteristics to the film. Thermal stability concerns how the deposited material holds up as later manufacturing operations expose it to heat. Area selectivity concerns where material is deposited on a patterned surface. Sample says those properties sit alongside flowability in the PECVD platform, while ASM says its levelling works across wafers with different densities of patterned features.

ASM targets three-dimensional chip structures

The intended application is a growing fabrication problem, in ASM’s account: as logic and memory devices acquire more complex three-dimensional structures, filling their features and keeping later layers level becomes harder. The company says sequences that use several filling, levelling and patterning operations increase risks to manufacturing yield and throughput. Vertos puts two of those operations into one process, though patterning remains a subsequent step.

Hichem M’Saad, ASM’s Chief Executive Officer, presents the material as part of the work required to keep scaling complex devices. He also links chips made with it to more efficient AI performance.

ASM says XP8 Vertos Flowable Carbon has begun deployment in high-volume manufacturing. The company describes it as applicable to both logic and memory devices, placing the process in the two device categories for which it says increasingly complex three-dimensional structures are making gap filling and surface control more demanding.

Topics: Chips, Manufacturing