At the Apsara Conference in Hangzhou on 22 September 2026, Alibaba’s semiconductor subsidiary T-Head announced Yitian 720 and Yitian 730 server CPUs slated for the third quarter of 2027 and a later Yitian 750 that will support its ICN inter-chip interconnect for direct attachment to Zhenwu AI accelerators, according to Pandaily.
Key points
- Yitian 720 and Yitian 730 server CPUs planned for Q3 2027; Yitian 730 uses a fully self-developed T-Head microarchitecture with single-core SPECint2017/GHz performance up to 1.4 times Yitian 710
- Yitian 750 will add ICN-link support, enabling direct CPU-to-accelerator connection without PCIe
- Zhenwu V900 AI chip unveiled with three times the performance of Zhenwu M890, 216GB memory, 1,200GB/s inter-chip bandwidth, native FP8 and FP4 support
- Zhenwu V900 mass production and commercial release scheduled for Q1 2027; scales to over 1,000 chips per supernode via ICN Switch
- Alibaba Cloud targets over 20GW global datacentre capacity by 2032
Yitian 730 moves to a fully self-developed core
The Yitian 730 marks the first generation in the line built on a CPU microarchitecture developed entirely by T-Head. The company claims single-core SPECint2017 per gigahertz performance up to 1.4 times that of the current Yitian 710. Secondary coverage from Chipsee and ifeng, cited by Pandaily, adds roadmap-level sketches: Yitian 720 positioned around 192 cores with 12-channel DDR and 96-lane PCIe at roughly 1.1 times the 710’s same-frequency SPECrate, and Yitian 730 around 32 self-developed cores with simultaneous multithreading, 8-channel DDR and 128-lane PCIe at 1.25 to 1.4 times. Those figures remain slideware targets until final datasheets appear.
ICN-link aims to replace PCIe between CPU and accelerator
The follow-on Yitian 750 is described as a second-generation self-developed core that supports T-Head’s ICN chip-to-chip link. Rather than attaching AI accelerators through conventional PCIe, the ICN protocol lets the CPU and Zhenwu chips share a direct interconnect. T-Head argues that more capable host chips remain necessary because these tasks continue to rely on CPUs for coordination, state management and data preparation alongside accelerators. The shift mirrors a broader industry move toward system-level AI infrastructure where chip-to-chip communication, memory capacity and network bandwidth become the limiting factors as model sizes grow.
Zhenwu V900 targets trillion-parameter scale
T-Head also unveiled the Zhenwu V900, its latest high-end AI chip for both training and inference. The company claims three times the performance of the predecessor Zhenwu M890, 216GB of memory and 1,200GB/s of inter-chip bandwidth. The V900 natively supports low-precision formats FP8 and FP4, which can improve efficiency for certain workloads and help reduce inference costs. T-Head uses its proprietary ICN Switch interconnect chips to connect multiple V900s into supernodes, providing native memory semantics and unified memory addressing across thousands of chips. The company says over 1,000 V900 chips can operate as one system, and that an AI installation combining them with Alibaba Cloud’s new network design can reach 500,000 accelerators.
Mass production and commercial release of the Zhenwu V900 are scheduled for the first quarter of 2027. Supernode servers built on the earlier Zhenwu M890 are now in broad commercial use and handle models exceeding 2 trillion parameters, such as Qwen 3.8 and Kimi K3, with these capabilities also offered to developers via Alibaba Cloud’s Bailian platform. According to T-Head, the Zhenwu line has already been adopted by over 650 business clients in fields such as self-driving vehicles, financial services, large model development, physical AI, energy and industrial production.
Datacentre capacity pledge frames the silicon roadmap
Alibaba Cloud pledged to grow its global datacentre capacity beyond 20GW by 2032, a figure announced alongside the chip roadmap. Streamline Feed reported that the six-year horizon places the build-out behind the current US construction pipeline, where Cushman & Wakefield estimated 37.7GW under construction last week, with projects such as Stargate promising 10GW by 2029 and Meta planning a 5GW campus. The same report quoted Alibaba Group CEO Eddie Wu describing the current volume of machine thinking as less than 3% of all human thinking, arguing the growth runway remains enormous even at 1,000 times human capacity. Streamline Feed noted that the decisive date for the supply chain is the Q1 2027 mass-production milestone, since the 20GW target only converts into compute if T-Head ships V900s at cluster scale.
Alibaba Group CEO Wu Yongming stated at the conference that T-Head anticipates growing yearly AI chip volumes as its offerings gain broader use. The company also showcased its full-stack chip solutions and held hands-on workshops around the T-Head SAIL software stack covering model training, inference and software optimisation at the Apsara Conference.
