ASML Holding and Taiwan Semiconductor Manufacturing Company are leading a group of chipmakers that will adapt High NA extreme ultraviolet lithography tools to print larger data-centre processors, according to a Reuters report published on 8 September 2026. The collaboration includes Nvidia, Intel, Samsung and SK Hynix and targets a pilot production line using larger masks by 2031, with high-volume manufacturing readiness by 2033.
Key points
- Current High NA EUV scanners use a smaller exposure field than standard EUV tools, limiting maximum die size for AI accelerators.
- ASML targets a larger-mask pilot line in 2031 and high-volume readiness in 2033.
- ASML CTO Marco Pieters said the changes could lift system productivity by roughly 40 per cent.
- TSMC plans to introduce High NA EUV into advanced-node high-volume production from 2030.
- The initiative addresses a supply-chain prerequisite for the next generation of massive AI chips from Nvidia, AMD and hyperscalers.
The mask-size constraint
High NA EUV is the next generation of lithography required for the most advanced process nodes. ASML’s current High NA tools have a smaller exposure field than the widely deployed standard EUV scanners, which constrains the maximum die size that can be printed in a single exposure. As AI accelerators grow to reticle limits and beyond, the smaller mask becomes a bottleneck for the chip supply chain that feeds Nvidia, AMD and hyperscale data-centre operators.
Roadmap and customer commitments
ASML said it will work with TSMC, Nvidia, Intel, Samsung and SK Hynix on the larger-mask adaptation. The company targets a pilot production line by 2031 and high-volume manufacturing readiness by 2033. TSMC, ASML’s largest customer for EUV systems, plans to introduce High NA EUV into advanced-node high-volume production from 2030, giving the Dutch equipment maker a committed lead customer for the current generation while the larger-mask derivative is developed.
Productivity claim and financial exposure
ASML chief technology officer Marco Pieters said the larger-mask changes could lift the productivity of these systems by roughly 40 per cent. The claim is a company estimate and has not been independently verified. If realised, higher throughput would improve the economics of High NA EUV for foundries, but the revenue contribution remains years away: TSMC’s High NA high-volume production starts in 2030, while the larger-mask variant reaches pilot in 2031 and high volume in 2033. Neither company has disclosed the development cost or the incremental price of the larger-mask tools.
What has to become true
For the roadmap to translate into equipment demand, three conditions must hold: AI accelerator die sizes must continue to grow beyond the current High NA exposure field, TSMC and other foundries must qualify the larger-mask process on schedule, and the 40 per cent productivity gain must materialise in volume production to justify the capital outlay. The next dated test point is TSMC’s 2030 High NA high-volume start, which will establish whether the current-generation tools meet yield and throughput targets before the larger-mask variant enters pilot.
